Tag Archives: Recurrent Neural Networks

Time series events recognition in embedded devices

Pau Gairí, Tomas Palleja, Marcel Tresanchez, Real-time recognition of multivariate event-based time series on embedded devices using recurrent neural networks: A practical study, Engineering Applications of Artificial Intelligence, Volume 182, Part 1, 2026,10.1016/j.engappai.2026.115787.

Real-time time-series recognition on embedded devices remains challenging due to limited computational resources and memory capacity, but also because of the operational constraints imposed by randomly triggered, event-driven sensing applications with variable duration. Most deep learning approaches rely on offline processing, complete-sequence inference, and pre-established deployment frameworks. In contrast, hardware-aware design along with recurrent architectures can distribute inference across the time-series evolution, enabling low latency solutions that better suit time-critical applications. This work combines recurrent neural networks with gated units and microcontroller-oriented processing to enable multivariate, event-based classification directly on embedded hardware. On one hand, a peripheral-driven approach for acquisition, preprocessing, and sample-rate adaptation is introduced, including real-time dynamic linearization and normalization strategies for incomplete time series. On the other hand, a lightweight deep recurrent architecture is tailored to the characteristics of each input and extended with a multi-objective output. Additionally, a dedicated multi-label dataset together with an automated clustering and labelling methodology enables an event-based training strategy with shared objectives that ensures stable inference and efficient memory usage on the device. The proposed methodology was evaluated across different architectural configurations, identifying optimal trade-offs between computational cost and classification accuracy. The on-device implementation shows that 32-bit floating-point inference using the microcontroller Floating-Point Unit avoids additional compression while preserving up to 99% of the best model performance. The optimized kernel achieves a macro F1-score (average of per-class harmonic means of precision and recall) of 0.840, while real-time validation under real application conditions confirms robust operation with a macro F1-score of 0.898.