Category Archives: Electronics

Using stochastic bits instead of binary logic

H. Li and Y. Chen, Hybrid Logic Computing of Binary and Stochastic, IEEE Embedded Systems Letters, vol. 14, no. 4, pp. 171-174, Dec. 2022 DOI: 10.1109/LES.2022.3170457.

Binary logic is applied internally to almost all digital signal processing and computer systems, because binary logic is direct implemented in CMOS circuits. Stochastic logic is achieved through its particular representation of data, which uses the probability of the logic level being ON to represent data. Stochastic logic computing is a type of logic computation based on stochastic bit stream instead of the binary numbers. This letter proposes a hybrid computing system of binary logic and stochastic logic, called hybrid logic. The study discusses how to generate hybrid logic circuits, and demonstrates the properties of hybrid logic circuits.

A particular application of quick detection of changes in a signal: detecting changes of voltage regimes in the electric distribution network

D. Macii and D. Petri, Rapid Voltage Change Detection: Limits of the IEC Standard Approach and Possible Solutions, IEEE Transactions on Instrumentation and Measurement, vol. 69, no. 2, pp. 382-392, Feb. 2020, DOI: 10.1109/TIM.2019.2903617.

Rapid voltage changes (RVCs) are power quality (PQ) events characterized by small and fast transitions between two steady-state root-mean-square (rms) voltage levels. RVCs occur quite often at the distribution level and are expected to be even more frequent in the future due to the increasing penetration of dynamic loads and renewable-based generators in the smart grid. Unlike other PQ events, RVCs are less critical, but also more difficult to detect than dips/sags and swells, due to their smaller voltage variations. Nevertheless, they can be harmful to generators’ control systems and electronic equipment in general. Moreover, they strongly affect flicker. The IEC Standard 61000-4-3:2015 clearly describes an algorithm for RVC detection. However, this approach is poorly characterized in the scientific literature. In fact, it suffers from some drawbacks. In this paper, some of them (e.g., rate-dependent detection limits and detection delays) are analyzed in depth. In addition, an alternative approach based on the estimation of the rate of change of rms voltage is proposed. Multiple simulation results show that the approach considered is more sensitive to noise, but also faster, especially when not so fast RVCs occur. Moreover, it allows measuring the rate of change of rms voltage, which is currently disregarded in the IEC Standard.

Estimating parameters of periodic signals that are sampled with just two levels (0/1) in magnitude

P. Carbone, J. Schoukens and A. Moschitta, Quick Estimation of Periodic Signal Parameters From 1-Bit Measurements, IEEE Transactions on Instrumentation and Measurement, vol. 69, no. 2, pp. 339-353, Feb. 2020, DOI: 10.1109/TIM.2019.2902023.

Estimation of periodic signals, based on quantized data, is a topic of general interest in the area of instrumentation and measurement. Although several methods are available, new applications require low-power, low-complexity, and adequate estimation accuracy. In this paper, we consider the simplest possible quantization, that is, binary quantization, and describe a technique to estimate the parameters of a sampled periodic signal, using a fast algorithm. By neglecting the possibility that the sampling process is triggered by some signal-derived event, sampling is assumed to be asynchronous, that is, the ratio between the signal and the sampling periods is defined to be an irrational number. To preserve enough information at the quantizer output, additive Gaussian input noise is assumed as the information encoding mechanism. With respect to the published techniques addressing the same problem, the proposed approach does not rely on the numerical estimation of the maximum likelihood function but provides solutions that are very close to this estimate. At the same time, since the main estimator is based on matrix inversion, it proves to be less time-consuming than the numerical maximization of the likelihood function, especially when solving problems with a large number of parameters. The estimation procedure is described in detail and validated using both simulation and experimental results. The estimator performance limitations are also highlighted.

Estimating aging of integrated circuits with machine learning

Ke Huang; Xinqiao Zhang; Naghmeh Karimi, Real-Time Prediction for IC Aging Based on Machine Learning, IEEE Transactions on Instrumentation and Measurement, Volume: 68, Issue: 12, Dec. 2019, DOI: 10.1109/TIM.2019.2899477.

Estimating the aging-related degradation and failure of nanoscale integrated circuits (ICs), before they actually occur, is crucial for developing aging prevention/mitigation actions and in turn avoiding unexpected in-field circuit failures. Real-time monitoring of IC operating conditions can be efficiently used for predicting aging degradation and in turn timing failures caused by device aging. The existing approaches only take some specific operating conditions (e.g., workload or temperature) into account. In this paper, we propose a novel method for real-time IC aging prediction by extending the prediction schemes to a comprehensive model which takes into account any time-variant dynamic operating conditions relevant to aging prediction. Using a machine learning prediction model and the notion of equivalent aging time, we show that our approach outperforms the existing methods in terms of aging-prediction accuracy under different scenarios of time-variant operating conditions.

Interesting review of time-to-digital converters with the state-of-the-art and applications

S. Tancock, E. Arabul and N. Dahnoun, A Review of New Time-to-Digital Conversion Techniques. IEEE Transactions on Instrumentation and Measurement, vol. 68, no. 10, pp. 3406-3417, DOI: 10.1109/TIM.2019.2936717.

Time-to-digital converters (TDCs) are vital components in time and distance measurement and frequency-locking applications. There are many architectures for implementing TDCs, from simple counter TDCs to hybrid multi-level TDCs, which use many techniques in tandem. This article completes the review literature of TDCs by describing new architectures along with their benefits and tradeoffs, as well as the terminology and performance metrics that must be considered when choosing a TDC. It describes their implementation from the gate level upward and how it is affected by the fabric of the device [field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)] and suggests suitable use cases for the various techniques. Based on the results achieved in the current literature, we make recommendations on the appropriate architecture for a given task based on the number of channels and precision required, as well as the target fabric.

Methods for estimating periods of noisy signals

W. Fan, Y. Li, K. L. Tsui and Q. Zhou, A Noise Resistant Correlation Method for Period Detection of Noisy Signals, IEEE Transactions on Signal Processing, vol. 66, no. 10, pp. 2700-2710, DOI: 10.1109/TSP.2018.2813305.

This paper develops a novel method called the noise resistant correlation method for detecting the hidden period from the contaminated (noisy) signals with strong white Gaussian noise. A novel correlation function is proposed based on a newly constructed periodic signal and the contaminated signal to effectively detect the target hidden period. In contrast with the conventional autocorrelation analysis (AUTOC) method, this method demonstrates excellent performance, especially when facing strong noise. Fault diagnoses of rolling element bearings and gears are presented as application examples and the performance of the proposed method is compared with that of the AUTOC method.

Another paper about this in the same issue: 10.1109/TSP.2018.2818080.

A microprocessor designed for real-time predictability and short WCETs

Schoeberl, M., Puffitsch, W., Hepp, S. et al, Patmos: a time-predictable microprocessor, Real-Time Syst (2018) 54: 389, DOI: 10.1007/s11241-018-9300-4.

Current processors provide high average-case performance, as they are optimized for general purpose computing. However, those optimizations often lead to a high worst-case execution time (WCET). WCET analysis tools model the architectural features that increase average-case performance. To keep analysis complexity manageable, those models need to abstract from implementation details. This abstraction further increases the WCET bound. This paper presents a way out of this dilemma: a processor designed for real-time systems. We design and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor. A method cache serves as the cache for the instructions and a split cache organization simplifies the WCET analysis of the data cache. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average-case performance.

Time synchronization (only offset) or power sinusoid signals

A. Mingotti, L. Peretto and R. Tinarelli, Accuracy Evaluation of an Equivalent Synchronization Method for Assessing the Time Reference in Power Networks, IEEE Transactions on Instrumentation and Measurement, vol. 67, no. 3, pp. 600-606, DOI: 10.1109/TIM.2017.2779328.

This paper deals with the evaluation of the accuracy performance of an approach for assessing the phase displacement between voltages at power network nodes. This task is accomplished by processing asynchronous measurements taken at each node. This turns into an equivalent synchronization, which is, therefore, obtained without exploiting any synchronization signals, such as the ones provided by means of wireless (i.e., global positioning system) or wired technologies. As a matter of fact, distribution system operators will gain the possibility of deploying, at more affordable costs, wide area measurement system (WAMS) over their power networks for enhancing their stability and reliability. Phasor measurement units (PMUs) are the most common examples of such WAMS, but, besides their high cost, there are circumstances where providing a time reference signal to remote PMUs often becomes a difficult task. This paper aims at recalling the basic theoretical principles of the method and at proving its applicability in power network through a deep analysis of its metrological performance.

Electronic circuit for harvesting energy autonomously in a multi-sensor device

Dias, P.C.; Morais, F.J.O.; de Morais Franca, M.B.; Ferreira, E.C.; Cabot, A.; Siqueira Dias, J.A., Autonomous Multisensor System Powered by a Solar Thermoelectric Energy Harvester With Ultralow-Power Management Circuit, in Instrumentation and Measurement, IEEE Transactions on , vol.64, no.11, pp.2918-2925, Nov. 2015, DOI: 10.1109/TIM.2015.2444253.

An autonomous multisensor system powered by an energy harvester fabricated with a flat-panel solar thermoelectric generator with an ultralow-power management circuit is presented. The multisensor system was tested in an agricultural application, where every 15 min the values of the temperature, air humidity, and solar radiation have to be measured and stored in a mass memory device (a Secure Digital card), with their respective time stamp. The energy-harvesting switching dc-dc converter is based on a low-input-voltage commercial integrated circuit (LTC3108), which charges a 1.65-F supercapacitor up to 5.0 V. A novel ultralow-power management circuit was developed to replace the internal power management circuitry of the LTC3108, and using this circuit, the operation of the system when no energy can be harvested from the environment is extended from 136 h to more than 266 h. The solar thermoelectric generator used for the energy harvesting is composed of a bismuth telluride thermoelectric generator with a 110-mV/°C Seebeck coefficient sandwiched between a 40 cm \times 40 cm anodized aluminum flat panel and an aluminum heatsink. On a sunny winter day in the southern hemisphere (12 August 2014, at Campinas, SP—Brazil, Latitude: 22° 54’), the energy supplied by the harvesting system to the supercapacitor was 7 J.