Category Archives: Real-time Systems

Clock synchronization in the CAN bus

M. Akp\u0131nar and K. W. Schmidt, Predictable Timestamping for the Controller Area Network: Evaluation and Effect on Clock Synchronization Accuracy, IEEE Transactions on Systems, Man, and Cybernetics: Systems, vol. 54, no. 3, pp. 1926-1935, March 2024 DOI: 10.1109/TSMC.2023.3332559.

Accurate timestamps are important for clock synchronization (CS) and cyber-security on the controller area network (CAN). This article proposes a new predictable timestamping (TS) method on CAN. Different from existing TS methods, our method reduces the effect of uncertainties that are caused by the CAN bit timing, oscillator drifts, and different cable lengths. Accordingly, our TS method provides an improved TS quality, which is confirmed in comprehensive hardware experiments. We further show the positive impact of our TS method on CS for CAN with clock accuracies below 100 ns.

Image resizing for achieving real-time in embedded AI

Hu, Y., Liu, S., Abdelzaher, T. et al. Real-time task scheduling with image resizing for criticality-based machine perception, Real-Time Syst 58, 430\u2013455 (2022) DOI: 10.1007/s11241-022-09387-6.

This paper extends a previous conference publication that proposed a real-time task scheduling framework for criticality-based machine perception, leveraging image resizing as the tool to control the accuracy and execution time trade-off. Criticality-based machine perception reduces the computing demand of on-board AI-based machine inference pipelines (that run on embedded hardware) in applications such as autonomous drones and cars. By segmenting inputs, such as individual video frames, into smaller parts and allowing the downstream AI-based perception module to process some segments ahead of (or at a higher quality than) others, limited machine resources are spent more judiciously on more important parts of the input (e.g., on foreground objects in lieu of backgrounds). In recent work, we explored the use of image resizing as a way to offer a middle ground between full-resolution processing and dropping, thus allowing more flexibility in handling less important parts of the input. In this journal extension, we make the following contributions: (i) We relax a limiting assumption of our prior work; namely, the need for a \u201cperfect sensor” to identify which parts of the image are more critical. Instead, we investigate the use of real LiDAR measurements for quick-and-dirty image segmentation ahead of AI-based processing. (ii) We explore another dimension of freedom in the scheduler: namely, merging several nearby objects into a consolidated segment for downstream processing. We formulate the scheduling problem as an optimal resize-merge problem and design a solution for it. Experiments on an AI-powered embedded platform with a real-world driving dataset demonstrate the practicality and effectiveness of our proposed framework.

Current state of the practical use of real-time systems, got through industry questionnaires

Akesson, B., Nasri, M., Nelissen, G. et al. A comprehensive survey of industry practice in real-time systems, Real-Time Syst 58, 358\u2013398 (2022) DOI: 10.1007/s11241-021-09376-1.

This paper presents results and observations from a survey of 120 industry practitioners in the field of real-time embedded systems. The survey provides insights into the characteristics of the systems being developed today and identifies important trends for the future. It extends the results from the survey data to the broader population that it is representative of, and discusses significant differences between application domains. The survey aims to inform both academics and practitioners, helping to avoid divergence between industry practice and academic research. The value of this research is highlighted by a study showing that the aggregate findings of the survey are not common knowledge in the real-time systems community.

For compilers to be WCET-aware

Heiko Falk, Paul Lokuciejewski, A compiler framework for the reduction of worst-case execution times, Real-Time Systems volume 46, pages251–300(2010), DOI: 10.1007/s11241-019-09337-9.

The current practice to design software for real-time systems is tedious. There is almost no tool support that assists the designer in automatically deriving safe bounds of the worst-case execution time (WCET) of a system during code generation and in systematically optimizing code to reduce WCET. This article presents concepts and infrastructures for WCET-aware code generation and optimization techniques for WCET reduction. All together, they help to obtain code explicitly optimized for its worst-case timing, to automate large parts of the real-time software design flow, and to reduce costs of a real-time system by allowing to use tailored hardware.

On the formalization and conceptualization of real-time basic concepts and methods (RMS, EDF) for robots

Nicolas Gobillot, Charles Lesire, David Doose, A Design and Analysis Methodology for Component-Based Real-Time Architectures of Autonomous Systems. Journal of Intelligent & Robotic Systems, October 2019, Volume 96, Issue 1, pp 123–138, DOI: 10.1007/s10846-018-0967-5.

The integration of autonomous robots in real applications is a challenge. It needs that the behaviour of these robots is proved to be safe. In this paper, we focus on the real-time software embedded on the robot, and that supports the execution of safe and autonomous behaviours. We propose a methodology that goes from the design of component-based software architectures using a Domain Specific Language, to the analysis of the real-time constraints that arise when considering the safety of software applications. This methodology is supported by a code generation toolchain that ensures that the code eventually executed on the robot is consistent with the analysis performed. This methodology is applied on a ground robot exploring an area.

Interesting review of time-to-digital converters with the state-of-the-art and applications

S. Tancock, E. Arabul and N. Dahnoun, A Review of New Time-to-Digital Conversion Techniques. IEEE Transactions on Instrumentation and Measurement, vol. 68, no. 10, pp. 3406-3417, DOI: 10.1109/TIM.2019.2936717.

Time-to-digital converters (TDCs) are vital components in time and distance measurement and frequency-locking applications. There are many architectures for implementing TDCs, from simple counter TDCs to hybrid multi-level TDCs, which use many techniques in tandem. This article completes the review literature of TDCs by describing new architectures along with their benefits and tradeoffs, as well as the terminology and performance metrics that must be considered when choosing a TDC. It describes their implementation from the gate level upward and how it is affected by the fabric of the device [field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)] and suggests suitable use cases for the various techniques. Based on the results achieved in the current literature, we make recommendations on the appropriate architecture for a given task based on the number of channels and precision required, as well as the target fabric.

A microprocessor designed for real-time predictability and short WCETs

Schoeberl, M., Puffitsch, W., Hepp, S. et al, Patmos: a time-predictable microprocessor, Real-Time Syst (2018) 54: 389, DOI: 10.1007/s11241-018-9300-4.

Current processors provide high average-case performance, as they are optimized for general purpose computing. However, those optimizations often lead to a high worst-case execution time (WCET). WCET analysis tools model the architectural features that increase average-case performance. To keep analysis complexity manageable, those models need to abstract from implementation details. This abstraction further increases the WCET bound. This paper presents a way out of this dilemma: a processor designed for real-time systems. We design and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor. A method cache serves as the cache for the instructions and a split cache organization simplifies the WCET analysis of the data cache. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average-case performance.

A new method for nonlinear optimization aimed to embedded computers, and a nice state of the art of that problem

N. Y. Chiang, R. Huang and V. M. Zavala, An Augmented Lagrangian Filter Method for Real-Time Embedded Optimization, IEEE Transactions on Automatic Control, vol. 62, no. 12, pp. 6110-6121, DOI: 10.1109/TAC.2017.2694806.

We present a filter line-search algorithm for nonconvex continuous optimization that combines an augmented Lagrangian function and a constraint violation metric to accept and reject steps. The approach is motivated by real-time optimization applications that need to be executed on embedded computing platforms with limited memory and processor speeds. The proposed method enables primal-dual regularization of the linear algebra system that in turn permits the use of solution strategies with lower computing overheads. We prove that the proposed algorithm is globally convergent and we demonstrate the developments using a nonconvex real-time optimization application for a building heating, ventilation, and air conditioning system. Our numerical tests are performed on a standard processor and on an embedded platform. We demonstrate that the approach reduces solution times by a factor of over 1000.

A novel method for hard real-time communications using the physical layer of Ethernet and a variation of TDMA

Andrzej Przybył, Hard real-time communication solution for mechatronic systems, Robotics and Computer-Integrated Manufacturing, Volume 49, 2018, Pages 309-316, DOI: 10.1016/j.rcim.2017.08.001.

The paper proposes a method to build a highly efficient real-time communication solution for mechatronic systems. The method is based on the Ethernet physical layer (PHY) and on field programmable gate array (FPGA) technology and offers a better performance when compared to commercially available communication solutions. Although it is not directly compatible with the OSI/ISO model of TCP/IP protocol, vertical integration is done with a gateway. This provides simplicity and safety. Moreover, the use of the FPGA allows for integrating the communication solution with the user algorithm of particular distributed device inside a single chip. Therefore, the proposed solution is efficient and highly integrated.

A new method to obtain WCET from binary code and to analyze the execution paths

Thomas Sewell, Felix KamGernot Heiser, High-assurance timing analysis for a high-assurance real-time operating system, Real-Time Systems, Volume 53, Issue 5, pp 812–853, DOI: 10.1007/s1124.

Worst-case execution time (WCET) analysis of real-time code needs to be performed on the executable binary code for soundness. Obtaining tight WCET bounds requires determination of loop bounds and elimination of infeasible paths. The binary code, however, lacks information necessary to determine these bounds. This information is usually provided through manual intervention, or preserved in the binary by a specially modified compiler. We propose an alternative approach, using an existing translation-validation framework, to enable high-assurance, automatic determination of loop bounds and infeasible paths. We show that this approach automatically determines all loop bounds and many (possibly all) infeasible paths in the seL4 microkernel, as well as in standard WCET benchmarks which are in the language subset of our C parser. We also design and validate an improvement to the seL4 implementation, which permits a key part of the kernel’s API to be available to users in a mixed-criticality setting.